After forming the individual device regions in a semiconductor substrate, the regions must be connected together to form an operative device that performs the desired circuit functions. This connection process is referred to as metallization and is performed using a number of different photolithographic and deposition techniques. The overall effectiveness of the metal interconnect system is governed by the resistivity, thickness, length and the total contact resistance of all the metal-region interconnects. The contact resistance at a metal-to-region interface is influenced by the materials employed, the substrate doping and the contact dimensions. The smaller the contact size, the higher the contact resistance. In modern semiconductor circuits the contact region is the dominant factor in the metal interconnect system performance.
One technique for forming a low contact resistance device employs a silicide layer on the device doped regions, such as the source/drain regions and polysilicon gate of a metal-oxide-semiconductor field effect transistor (MOSFET). This practice has become increasingly important for very high density devices where the feature size, and thus the contact area, is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity and the contact resistance of source/drain regions and polysilicon gates, increases the effective contact area, and provides an etch stop layer during subsequent processing steps.
A common technique employed in semiconductor manufacturing to form the silicide contact is self-aligned silicide (“salicide”) processing. Salicide processing involves the deposition of a metal that forms intermetallic bonds with the silicon (Si), but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), tungsten (W), molybdenum (Mo) and nickel (Ni). Generally, refractory metals are used to form the silicide. These metals form low resistivity phases with silicon, such as TiSi2, CoSi2 and NiSi.
To form the silicide, the metal is deposited with a uniform thickness across the entire semiconductor wafer, by for example, using a physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, direct current magnetron sputtering system. The deposition is performed after gate etch and source/drain junction formation. The deposited metal blankets the polysilicon gate electrode, the oxide spacers between the gate and the source/drain regions, and the oxide isolation regions between devices. A cross-section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with the prior art techniques is depicted in FIG. 1.
As shown in FIG. 1, a n-type MOSFET 8 is formed within a silicon substrate 10, comprising a p-type well 11, lightly doped (n−) source/drain regions 12/14, source/drain regions (n+) 16/18, and a polysilicon gate 20 formed over a gate oxide 22. Oxide spacers 24 are formed on the sides of the polysilicon (n+ type) gate electrode 20. A refractory metal layer 30, comprising cobalt, for example, is blanket deposited over the source/drain regions 16/18, the polysilicon gate 20 and the spacers 24. The metal layer 30 also blankets silicon dioxide isolation regions 32 that isolate adjacent devices.
A first rapid thermal anneal (RTA) is then performed at a temperature of between about 450° to 700° C. for a short period in a nitrogen atmosphere. The nitrogen reacts with the metal to form a metal nitride at the top surface 33 of the metal 30, while the metal reacts with the underlying silicon, forming a metal silicide. Hence, the reaction of the metal with the silicon forms a silicide region 40 within the gate 20 and silicide regions 41 within the source/drain regions 16/18, as depicted in FIG. 2. Typically, about one-third of the underlying silicon is consumed during the formation of the metal silicide.
After the first rapid thermal anneal step, any unreacted metal is stripped away by a wet etch process that is selective to the metal silicide. The resultant structure is illustrated in FIG. 3. The substrate 10 is subjected to a second, higher temperature rapid thermal anneal step, for example above 700° C., to change the stochiometry of the metal silicide, forming a lower resistance metal silicide by converting the higher resistivity metal silicide to a lower resistivity phase. For example, when the metal is cobalt, the higher resistivity phase is Co2Si and the lower resistivity phase is CoSi2.
As described above, when the polysilicon and doped source/drain regions are both exposed to the metal, the silicide forms simultaneously over both regions. Thus, this method is described as a “salicide” process since the silicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.
One of the concerns associated with cobalt silicide technologies is junction leakage, which occurs when cobalt silicide is formed such that it extends nearly to the bottom of the source/drain region 16/18. The distance between the cobalt silicide layer 41 and the bottom of the source/drain region 16/18 is identified by a reference character 50 in FIG. 3. A cause of this problem is high silicon consumption during the silicide formation process. One solution for overcoming this problem is to make the doped source/drain regions 16/18 deeper. However, this is counter to the preferred extremely shallow source and drain regions that support device scaling. Also, the deeper device regions negatively impact device performance.
Leakage also occurs due to incomplete removal of the unreacted metal from the spacers 24 and the oxide isolation regions 32. As a result, gate-to-substrate and region-to-region leakage currents flow through the unreacted metal. Also, prolonged anneal cycles, used to ensure reaction between the metal and the underlying silicon, can result in the formation of metal silicide ribbons on the surface of the silicon dioxide regions 32, again creating a path for the flow of leakage currents.
It is known that the sheet resistance of the silicide layer 40/41 is an inverse function of the layer thickness. It is also known that the degree of roughness at the interface between the silicide layer 40/41 and the underlying silicon device region, such as the source/drain regions 16/18, influences current leakage. To achieve a preferred sheet resistance, a thicker silicide layer may be required. However, if the silicide layer 41 is made too thick, the distance 50 decreases, thereby increasing the likelihood of leakage current flow between the source/drain regions 16/18 and the p-type well 11. Further, increased roughness of the interface also increases leakage current. It is therefore advantageous to form a silicide layer with reduced surface roughness.
According to the prior art, a capping layer, for example a titanium layer, is formed over the cobalt layer before the first RTA step, to reduce the aforementioned surface roughness.